The term logic array, as used in this application, means read-only memories (ROM's), programmed logic arrays (PLA's) and random access read-write memories (RAM's). In the read-only memory (ROM) to be described, the level of the output voltage at the output node is dependent upon the ratio of the load impedance of the output circuit and the impedance of the output circuit and the impedance of the network of the array. Such networks are arranged in conductive columns and rows with field-effect transistors selectively located in accordance with the data to provide a current path between two columns which are selected in response to signals on row conductors. A logic array having such an arrangement is described in U.S. Pat. No. 3,618,050, issued Nov. 2, 1971, to R. H. Heeren and entitled "Read-Only Memory Arrays In Which A Portion of the Memory-Addressing Circuitry is Integral to the Array."
An integrated circuit logic array exhibits considerable distributed resistance and parasitic capacitance. Current flows through a relatively high load impedance and is switched to the supply return in a predetermined sequence by the transistor network. The output voltage level from the array is determined by the current path through the network. The network, when in its conductive state, has considerable resistance; therefore, a relatively high load impedance is used to assure that the output voltage will fall to a sufficiently low level for all possible paths through the network. The array capacitance and external load capacitance are quite large. These capacitances are in parallel with the output node of the array and when combined with a high load resistance, produce a long charge rate time constant which adversely affects the speed of the array. One attempt at reducing the effect of capacitance on the switching speed of a ratioed logic array is described in U.S. Pat. No. 3,944,848 issued Mar. 16, 1976, to R. H. Heeren and entitled "Voltage Sensitive Isolation for Static Logic Circuit." Certain features of this reference are included in the illustrated embodiment.